1. Field of the Invention
The present invention relates to a device capable of setting, in a program, internal functions, and to a computer and data processing apparatus using such a device, and more specifically to a data processing system having a device, a computer, and a data processing apparatus capable of performing a flexible operation by dynamically setting and modifying internal functions.
2. Description of the Related Art
The computer industry owes its recent progress to mainframes and personal computers of reduced size, and it has been attained by greatly increasing the power per unit price of a processor. The current processor architecture is designed to process a program described using commands each of which has a basic length, and a high-speed process has been realized by shortening the execution cycle of a computer.
Under such circumstances, clock speed of a processor is getting faster and faster. When the clocks signals of most modern processors running at several hundreds of MHz are used, it is required to apply up-to-date process technology to reduce the area of a chip in consideration of the delaying of a clock signal, thereby enormously increasing the time and cost spent on computer development. As a result, a new computer paradigm, that is, a basic configuration, has been demanded.
When a process is performed, the same processor architecture is normally used for all algorithms only for convenience. If a process can be performed using architecture appropriate for each algorithm, that is, a required process, then a high-speed process can be expected independent of the conventional method which depends on a high clock speed.
The architecture according to this concept is a VLIW (very long instruction word) architecture which is considered to be the architecture of the next generation of microprocessors. This type of architecture has been adopted in a super parallel computer, an ASIC product, etc.
FIG. 1 shows an example of the configuration of a VLIW architecture. In FIG. 1, the architecture includes n issue slots 101 for determining the number of instructions executed in parallel; n function units 102, for example, ALUs, which correspond one-to-one to the n function units 102; a register file 103; and a read/write cross bar 104 for controlling the read/write of data from the function units 102 to the register file 103.
In the above described architecture, a plurality of instructions are issued in each clock cycle, and the plurality of instructions are executed in parallel by the n issue slots 101. At this time, a plurality of instructions to be simultaneously executed are assumed to be preliminarily selected, and the plurality of instructions are statically regarded by a compiler as a very long instruction (VLI). Therefore, no scheduling circuit is required. Furthermore, since the read/write cross bar 104 is used, it is not necessary to connect each function unit 102 to the register file 103.
Thus, the VLIW architecture more freely determines the length of an instruction than a conventional processor architecture, and therefore can perform a parallel process. However, it also has the problem that its intrinsic throughput cannot be fully utilized because a target algorithm should be replaced with prepared instructions or the width of the data bus is limited during the process. Therefore, circuit elements are required to more freely configure a function unit or connect a register file, and much attention is paid to the circuit elements capable of implementing functions through a program such as a programmable logic array (PLA), a field programmable gate array (FPGA), etc.
With these PLA and FPGA, a logic circuit and interconnecting wiring can be freely designed, but an area for storing a function and an area for selecting the connection of lines are required. Therefore, the PLA and the FPGA are inferior in integration to the ASIC, and can hardly be applicable to a central portion such as an ALU, etc. Since they are formed by the smallest possible number of logic cells and connection resources for connecting the cells, and a function is set only once before the operation, it is hard to set or modify a function through operations.